math_ext.cu

/*
 Copyright (c) 2021-2023, The Neko Authors
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     copyright notice, this list of conditions and the following
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     with the distribution.
 
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     contributors may be used to endorse or promote products derived
     from this software without specific prior written permission.
 
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 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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 BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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*/
 
#include "math_ext_kernel.h"
#include <device/cuda/check.h>
#include <device/device_config.h>
#include <stdio.h>
#include <stdlib.h>
 
extern "C" {
 
#include <math/bcknd/device/device_mpi_op.h>
#include <math/bcknd/device/device_mpi_reduce.h>
 
void cuda_copy_mask(void* a, void* b, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    copy_mask_kernel<real><<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
        (real*)a, (real*)b, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
void cuda_cadd_mask(void* a, real* c, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    cadd_mask_kernel<real><<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
        (real*)a, *c, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
void cuda_invcol1_mask(void* a, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    invcol1_mask_kernel<real>
        <<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
            (real*)a, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
void cuda_col2_mask(void* a, void* b, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    col2_mask_kernel<real><<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
        (real*)a, (real*)b, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
void cuda_col3_mask(
    void* a, void* b, void* c, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    col3_mask_kernel<real><<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
        (real*)a, (real*)b, (real*)c, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
void cuda_sub3_mask(
    void* a, void* b, void* c, int* size, int* mask, int* mask_size) {
 
    const dim3 nthrds(1024, 1, 1);
    const dim3 nblcks(((*mask_size) + 1024 - 1) / 1024, 1, 1);
 
    if (*mask_size == 0) return;
    sub3_mask_kernel<real><<<nblcks, nthrds, 0, (cudaStream_t)glb_cmd_queue>>>(
        (real*)a, (real*)b, (real*)c, *size, mask, *mask_size);
    CUDA_CHECK(cudaGetLastError());
}
}